{"id":235,"date":"2021-06-24T10:16:51","date_gmt":"2021-06-24T01:16:51","guid":{"rendered":"https:\/\/derrylab.com\/?p=235"},"modified":"2021-06-24T10:18:25","modified_gmt":"2021-06-24T01:18:25","slug":"this-makes-my-risc-v-trap-handler-does-not-work","status":"publish","type":"post","link":"https:\/\/blog.derrylab.com\/index.php\/2021\/06\/24\/this-makes-my-risc-v-trap-handler-does-not-work\/","title":{"rendered":"This Makes My RISC-V Trap Handler Does Not Work"},"content":{"rendered":"\n

I was working on a RISCV assembly when suddenly I got a weird issue.

The exception does not get caught in the trap handler. I thought this was a QEMU bug on the RISCV target because the trap handler works on my other code.

Then after a day of digging, I figured out that it was the mtvec<\/code> needs to be aligned on 4-byte, as mentioned on the privileged ISA<\/a>.<\/p>\n\n\n\n\n\n\n\n

The value in the BASE field must always be aligned on a 4-byte boundary, and the MODE setting may impose additional alignment constraints on the value in the BASE field<\/p><\/blockquote>\n\n\n\n

Finally, simply by replacing the value of mtvec<\/code> with a multiple of 4-bytes, the exception can be trapped by the trap handler and functioning properly.<\/p>\n","protected":false},"excerpt":{"rendered":"

I was working on a RISCV assembly when suddenly I got a weird issue. The exception does not get caught in the trap handler. I thought this was a QEMU bug on the RISCV target because the trap handler works on my other code. Then after a day of digging, I figured out that it […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[5],"tags":[100,98,101,33,86,102,103],"class_list":["post-235","post","type-post","status-publish","format-standard","hentry","category-programming","tag-asm","tag-assembly","tag-exception","tag-issue","tag-riscv","tag-trap-handler","tag-trap-vector"],"jetpack_featured_media_url":"","jetpack-related-posts":[{"id":244,"url":"https:\/\/blog.derrylab.com\/index.php\/2021\/03\/12\/the-riscv-isa-documentation-is-better-than-riscv-green-card\/","url_meta":{"origin":235,"position":0},"title":"The RISCV ISA Documentation Is Better than RISCV Green Card","author":"derry","date":"March 12, 2021","format":false,"excerpt":"I hosted the RISCV ISA Documentation. This is really helpful if you want to learn about the assembly syntax or learning the RISCV itself. As a beginner, this documentation is more effective instead of constantly checking at the green card. :) RISCV ISA Documentation:https:\/\/blog.derrylab.com\/riscv-isa-documentation You can host it yourself, it\u2026","rel":"","context":"In "linux"","block_context":{"text":"linux","link":"https:\/\/blog.derrylab.com\/index.php\/category\/linux\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]},{"id":146,"url":"https:\/\/blog.derrylab.com\/index.php\/2020\/12\/29\/arty-a7-riscv-debugging-using-j-link\/","url_meta":{"origin":235,"position":1},"title":"Stuck at Debugging RISCV on Arty A7 using J-Link","author":"derry","date":"December 29, 2020","format":false,"excerpt":"Running the RISCV Processor I got an Arty A7 board coming to my desk, and I'm curious to try running a RISCV processor on it. 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The other interesting alternative to try is VexRiscv, and everyone keeps posting about Arty A7 35T while\u2026","rel":"","context":"In "linux"","block_context":{"text":"linux","link":"https:\/\/blog.derrylab.com\/index.php\/category\/linux\/"},"img":{"alt_text":"","src":"https:\/\/i0.wp.com\/blog.derrylab.com\/wp-content\/uploads\/2022\/03\/pexels-rone-ferreira-3690005-1-scaled.jpg?fit=1200%2C800&ssl=1&resize=350%2C200","width":350,"height":200,"srcset":"https:\/\/i0.wp.com\/blog.derrylab.com\/wp-content\/uploads\/2022\/03\/pexels-rone-ferreira-3690005-1-scaled.jpg?fit=1200%2C800&ssl=1&resize=350%2C200 1x, https:\/\/i0.wp.com\/blog.derrylab.com\/wp-content\/uploads\/2022\/03\/pexels-rone-ferreira-3690005-1-scaled.jpg?fit=1200%2C800&ssl=1&resize=525%2C300 1.5x, https:\/\/i0.wp.com\/blog.derrylab.com\/wp-content\/uploads\/2022\/03\/pexels-rone-ferreira-3690005-1-scaled.jpg?fit=1200%2C800&ssl=1&resize=700%2C400 2x, https:\/\/i0.wp.com\/blog.derrylab.com\/wp-content\/uploads\/2022\/03\/pexels-rone-ferreira-3690005-1-scaled.jpg?fit=1200%2C800&ssl=1&resize=1050%2C600 3x"},"classes":[]},{"id":2242,"url":"https:\/\/blog.derrylab.com\/index.php\/2022\/10\/18\/how-to-do-buffer-overflow-attack-on-64bit-machine\/","url_meta":{"origin":235,"position":3},"title":"How to Do Buffer Overflow Attack on 64bit Machine","author":"derry","date":"October 18, 2022","format":false,"excerpt":"Professor's course material was out of date. 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The installer was stuck and gives me an error message: ibndias@shaheen:~\/Downloads$ .\/Xilinx_Unified_2020.1_0602_1208_Lin64.bin Verifying archive integrity... All good. Uncompressing Xilinx Installer............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... 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